المنشورات و المؤلفات
This paper presents an efficient HW/SW Codesign
FPGA-based architecture of B-ACOSD CFAR target detector in
log normal distribution for radar system. All CFAR system
modules are analyzed in order to identify the critical ones to be
optimized so that...
This paper presents a practical design exploration for a new application related to real-time, high-resolution target detection for radar systems. In this paper, an embedded architecture that combines the hardware and software components in a single...
This paper presents field-programmable gate array (FPGA)-based novel forward and backward automatic censored cell algorithms using a Nios II core processor embedded on a Stratix II FPGAprogrammable device. These algorithms were recently presented...