One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature
of their iterative belief propagation decoding, making them amenable to efficient hardware implementation.
However, for an arbitrary code construction, the random-like connections between the code’s
Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads
to complex interconnect wiring and routing congestion. In this paper, we present a novel LDPC code design