Window-constrained interconnect-efficient progressive edge growth LDPC codes
El-Maleh, Aiman H. . 2013
One of the attractive features of low-density parity-check (LDPC) codes is the parallel iterative nature
of their iterative belief propagation decoding, making them amenable to efficient hardware implementation.
However, for an arbitrary code construction, the random-like connections between the code’s
Tanner graph variable and check nodes makes fully-parallel implementation a difficult task as this leads
to complex interconnect wiring and routing congestion. In this paper, we present a novel LDPC code design
approach, based on the progressive edge growth (PEG) Tanner graph construction, to solve the problem
of dense connections between processing nodes. The approach is based on controlling the maximum connection
length between processing nodes in order to make fully parallel implementation feasible. The
proposed algorithm offers a good compromise between error correction performance and decoder complexity.
Simulation results and FPGA-based implementation comparisons are presented to demonstrate
the advantages of the proposed LDPC code constructions, and it is shown that, with proper windowconstrained
node placement design, an improvement of up to 40% in interconnect efficiency is achievable
without any significant degradation in error correction capability.
The paper presents a novel approach to reduce the bit error rate (BER) in iterative belief propagation (BP) decoding of low density parity check (LDPC) codes.
This paper presents a novel approach for the design and implementation of a simulation platform for evaluating LDPC codes performance. The existing LDPC code simulation tools consume very long…
The paper presents a novel approach to increase the performance and/or throughput of iterative belief propagation (BP) decoding of low density parity check (LDPC) codes. The proposed approach is…